Along with the trend of ever larger scale integration of semiconductor devices and reductions in chip size, miniaturization of metal lines and multi-layer wiring is accelerating. In a logic device having a multi-layer wiring structure, wiring delay is an important component of an overall device signal delay. The wiring delay is in proportion to a product of wiring resistance and wiring capacitance. Reducing the wiring resistance and capacitance reduces the wiring delay.
To reduce the wiring capacitance, a metal line may be formed of a copper material having a low resistance instead of an aluminum. It is, however, extremely difficult to simply pattern Cu to form the metal line. A damascene process may be used, in which an opening such as a wiring groove or a connection hole (via-hole) in an insulating film is filled with copper to form a metal line.
When a copper metal line is formed by a damascene process, a diffusion barrier film is formed to cover the inner wall of the opening with a metal seed layer before filling in the opening with copper to prevent copper from being diffused into the insulating film. The metal seed layer for a diffusion barrier film employs metal such as Ta or W having a high insulating value and a high melting point. Along with the trend of miniaturization of the Cu metal line, there is a drawback of increasing the RC delay of Back End Of Line (BEOL) wiring due to a relatively high effective dielectric value (k) of the diffusion barrier film. Particularly, when a highly miniaturized wiring layer including a via hole having a diameter of approximately 0.1 μm and a metal line having a width of approximately 0.1 μm employs metal such as Ta or W having a high melting point, there is a drawback of considerably increasing the wiring resistance and contact resistance.